A Network on a Chip (NOC) is a novel integrated circuit that applies a network architecture to a single chip to create a unique processing unit. Rather than utilizing a standard single von Neumann architecture, which has a control unit that coordinates data flowing between an arithmetic logic unit and memory, and between the arithmetic logic unit and input/output buffers along system input/output (I/O) busses, a NOC passes data between a plurality of integrated processor blocks (each of which may utilize a von Neumann-type processor) using packets. Each packet includes a header, which addresses the processor block that is to receive and process the packet, and a payload generally including one or more data words. In order to increase data transmission speeds between processor blocks, the data to be transmitted is generally packed into the packets prior to transmission and unpacked prior to execution at a logic node. In conventional systems data words are packed for transmission by removing spaces between the data words in the packet so that the data packets include “unaligned” data words, and prior to execution, the data words are re-aligned, i.e., the removed spaces are re-inserted in the appropriate locations. However, in conventional systems the packing and unpacking of the packets generally decreases efficiency of the processor blocks.
Therefore, a significant need continues to exist in the art for improving the performance of transferring and processing data packets.